Intel Secures Major Advanced Packaging Deal: SK Hynix to Adopt EMIB Technology for Next-Gen HBM

Source：TPCA　Updated Time：2026/08/26

Intel has scored another victory in its aggressive push into advanced packaging. South Korean memory giant SK Hynix revealed that it will incorporate Intel’s EMIB (Embedded Multi-die Interconnect Bridge) advanced packaging technology into its next-generation High Bandwidth Memory (HBM). Having previously relied exclusively on TSMC’s CoWoS (Chip-on-Wafer-on-Substrate) advanced packaging, SK Hynix’s decision to join the Intel camp has drawn significant industry attention.

SK Hynix joins other major players like Apple and MediaTek as another top-tier TSMC client opting for Intel’s advanced packaging technology. Industry analysts believe this shift is primarily driven by spillover demand resulting from severe capacity constraints in TSMC’s CoWoS supply chain.

However, SK Hynix holds a dominant position in AI memory and is currently one of the hottest companies in the tech sector. Its entry into Intel’s advanced packaging ecosystem considerably strengthens Intel’s foothold, prompting close industry observation of the future competitive dynamics between Intel and TSMC. While Intel’s foundry business has yet to secure landmark external clients for wafer fabrication, gaining momentum in advanced packaging could prove pivotal for unlocking broader strategic collaborations down the line.

According to combined foreign media reports, SK Hynix unveiled its 2.5D advanced packaging roadmap during the 2026 Hot Chips conference. Alongside TSMC’s CoWoS-L, CoWoS-R, and CoWoS-S solutions, the company explicitly listed Intel’s EMIB packaging technology. Furthermore, SK Hynix indicated that it is setting its sights on future 3D integration technologies.

During the conference, SK Hynix also detailed its next-generation HBM technical roadmap. Beyond doubling the I/O count for HBM4 from 1,024 to 2,048, the company plans to advance by increasing Through-Silicon Vias (TSVs), adopting hybrid bonding, and transitioning from 2.5D to 3D integration.

Reports highlighted that Jaesik Lee, Vice President of Packaging Engineering at SK Hynix, explained how the company intends to leverage advanced packaging technology to accelerate the execution of its HBM roadmap.

SK Hynix noted that the ongoing pursuit of higher power density, broader bandwidth, and taller stack heights in HBM technology—driven by thicker dielectric layers and denser TSVs—presents significant thermal, mechanical, and packaging challenges.

Industry insiders analyze that when Intel previously introduced its EMIB 2.5D solution, it featured an "EMIB-T" variant that integrates TSV technology to enhance vertical power delivery and support design migration from other packaging architectures. This aligns precisely with SK Hynix’s announced direction of doubling I/O counts and increasing TSV density for HBM4, serving as a primary factor behind SK Hynix’s adoption of Intel’s EMIB technology.

Additionally, Intel’s EMIB 2.5D architecture utilizes small embedded silicon bridges combined with multi-layer interconnects to replace the large silicon interposers required by competing solutions. Designed for HBM integration, it is promoted as ideal for modern AI applications by providing high-bandwidth, low-latency die-to-die connectivity, more flexible chiplet configurations, lower costs, and reduced manufacturing complexity.

Intel’s EMIB-T had previously secured a landmark ASIC design win with MediaTek. Now, with SK Hynix publicly naming Intel as a 2.5D advanced packaging partner for its HBM roadmap, this move holds profound significance for the future trajectory of the global advanced packaging market. (Source: Economic Daily News)

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